Semiconductor memory devices, such as EEPROMS, EPROM, and flash memory, contain an array of programmable memory cells. Memory cells are programmed using different voltage levels, e.g., to write data into a memory cell, a relative high voltage level is applied to the memory cell. At the same time, a lower voltage level may be applied to other memory cells not being written to prevent disturbing the current data in the memory cells. The actual voltage levels required to program memory cells may vary depending on the types of memory devices. To apply different voltage levels to the memory cells, decoders with level shifter circuits may be used. Each decoder has several level shifter circuits, wherein one level shifter controls one set of memory cells. Depending on the desired programming function to be performed on a memory cell, the level shifter in the decoder will select the proper voltage level to program that memory cell.
In the prior art, a level shifter may be implemented using switching transistors. The switching transistors can select the desired output voltage level from two different voltage sources. For example, a high voltage source that provides a relatively high voltage level and a low voltage source that provides a lower voltage level, and both voltage sources provide voltage levels that ramp gradually from the low end of the range to the high end. For example, the low voltage source may provide voltage ranging from 0 to 7 volts, whereas the high voltage source may provide voltage level that ramps from 5 to 16 volts. Each level shifter is connected to a common set of high and low voltage sources. Depending on the programming function to be performed, each level shifter may select a different voltage source. In operation, regardless which voltage source is selected by a particular level shifter, both voltage sources will concurrently ramp up their respective voltage levels at the same rate in order to supply voltages to all of the level shifters. When the voltage sources ramp up, the voltage in the level shifter will change, thus affecting the switching state of the transistors. To maintain the state of the switching transistors, a pull-up transistor may be used to provide the necessary additional voltage to the switching transistors when the voltage sources are ramping up. Because of the relatively high voltage differential between the voltage sources, the pull-up transistor encounters a high voltage potential (or breakdown voltage) across its drain and substrate regions, which is commonly referred to as the break down voltage margin across the drain and source or BVDSS margin. Transistors having a high BVDSS margin are more difficult to manufacture and are more costly, because the manufacturing process requires low tolerances and high precision. Typically, for such transistors, the rejection rate is high and the yield rate is relatively low. Therefore, it would be a cost benefit to be able to utilize level shifters having pull-up transistors with lower BVDSS margin.